This invention relates to a digital signal processing circuit for subjecting digital signal data to a digital signal processing and outputting the processed data after digital-to-analog conversion and, more particularly, to a digital signal processing circuit capable of preventing ocurrence of noise in an output of a digital-to-analog converter due to linearity adjustment therein.
A digital-to-analog converter of N bits is constructed in such a manner that weighted N current sources are turned on and off with respective bit signals of digital signal data and outputs of these current sources are added together and subjected to current-to-voltage conversion. Among the current sources, one corresponding to MSB (the most significant bit) is of the largest current value and this current source is utilized for adjusting linearity of the digital-to-analog converted output.
The adjustment of linearity of a digital-to-analog converter will be briefly described with reference to FIG. 7. Characteristics of components such as a current-to-voltage converting amplifier in a digital-to-analog converter often have an insensitive region in the vicinity of a zero-crossing point as shown in FIG. 7(a). By altering current value of MSB as shown in FIG. 7(b), the current value becomes one as shown in FIG. 7(c) and linearity of the conversion output thereby is improved. In other words, distortion component as a whole is minimized by this adjustment. This adjustment, however, causes, in most cases, the current value of MSB to be deviated from a value which is proper to MSB with a result that an error in MSB itself becomes large.
In digital data relating to positive and negative inputs such as 2's complement signal and offset binary signal in which MSB is inverted at a boundary between a positive region and a negative region, this error in MSB causes deterioration in signal-to-noise ratio when an original analog signal of a small level is applied.
Even when the input level of an original analog signal is zero, there is actually produced a background noise as shown in FIG. 2(a) in the original analog signal and this background noise fluctuates between small positive and negative values. Due to this background noise, the MSB output of the analog-to-digital converter fluctuates as shown in FIG. 2(b) and, when this output is digital-to-analog converted, the MSB error due to the linearity adjustment is added to the background noise as shown in FIG. 2(c) so that the noise level increases with resulting deterioration in the signal-to-noise ratio. Alternatively stated, if the value of MSB current is changed for the linearity adjustment, the signal-to-noise ratio of a digital-to-analog converter is changed as shown by a curve .circle.a in FIG. 3. At a point at which the signal-to-noise ratio is the best, the amount of noise is reduced to -6 dB. A digital-to-analog converted output which has the best signal-to-noise ratio with respect to the background noise of FIG. 2(a) is shown in FIG. 2(d). The linearity of the digital-to-analog converter output, however, generally hardly becomes the best at the best point of the signal-to-noise ratio and the best linearity generally causes deterioration in the signal-to-noise ratio.
For solving this problem, a digital signal processing circuit may be so constructed that a positive or negative analog DC offset is imparted to an input original analog signal when the original analog signal is of a small level so as to prevent a minute fluctuation due to background noise component from causing change in MSB in an analog-to-digital converted output. In this circuit, as shown in FIG. 4, a constant DC offset is imparted to an analog input by a mixer 14 and the analog input is converted to digital signal data by an analog-to-digital converter 10. This digital signal data is processed in a manner as required and thereafter is converted to an analog signal again by a digital-to-analog converter 16 and delivered out.
According to this circuit, the background noise which is produced during inputting of an original analog signal of a zero level has a smaller possibility of crossing the zero level owing to the DC offset imparted thereto as shown in FIG. 5(a) and, accordingly, the MSB output of the analog-to-digital converter 10 has a smaller possibility of being inverted as shown in FIG. 5(b) so that increase in the noise is prevented as shown by line .circle.b in FIG. 3 when the MSB linearity adjustment is performed in the digital-to-analog converter 16 which receives this digital signal data.
Even when noise of a relatively large magnitude occurs and crosses the zero level, it is so seldom that the signal-to-noise ratio as a whole is not significantly affected.
As the input level of an original analog signal increases, an original analog signal waveform comes to cross the zero level periodically. This however does not take place constantly as in the case of the background noise shown in FIG. 2(a) but it occurs at a long interval. Besides, this occurs when the signal component in the signal-to-noise ratio has become substantially large. Accordingly, such crossing of the zero level by the original analog signal does not significantly affect the signal-to-noise ratio.
Therefore, even if the MSB error is produced due to the linearity adjustment, it is possible to prevent the signal-to-noise ratio from deteriorating by imparting the DC offset to an original analog input in an analog stage before analog-to-digital conversion as shown in FIG. 4.
In recently developed digital signal processings performed in a digital signal processing section for processing a digital audio signal and other digital signals, processings involving change in frequency characteristics such as digital filtering and digital equalizing are increasing. In these processings, DC components are often cut off from digital signal data.
This poses the problem on the circuit as shown in FIG. 4 that, even if the DC offset is imparted to an original analog signal, this DC offset is cut off in the process of subsequent digital signal processing with a result that the effect of imparting of the DC offset is not obtained and deterioration in the signal-to-noise ratio occurs in the digital-to-analog converter 16 particularly during inputting of an original analog signal of a small level.
It is, therefore, an object of the invention to provide a digital signal processing circuit in which an offset component is not cut off even during a digital signal processing which involves change in frequency characteristics and thereby causes DC components to be substantially cut off so that adjustment of linearity can be made without causing deterioration in the signal- to-noise ratio of a digital-to-analog converter provided on the output side.